According to industry consultants, over 80% of multi-layer PCB designs are high-speed, needing special design strategies addressing high-speed effects to ensure successful operation. This trend will continue in the coming years with the introduction of new low voltage technologies, increased board density, faster edge rates, and shorter development cycles.
To help our clients to meet this challenge, we offer new methodologies to ensure the designs will work as desired, fulfilling all signal quality and timing demands. Working to old 'rules of thumb' is no-longer adequate to meet these requirements, so in order to be successful, we offer open access to the CADSTAR suite of simulation capabilities.
CADSTAR SI Verify is a solution that offers a complete pre and post-layout signal integrity simulation toolset, seamlessly integrated into CADSTAR. It uses an accurate transmission line simulation approach to analyse reflection and crosstalk effects, and to calculate the relevant timing information and delays. It can be used interactively by clients for selected nets as well as in batch-mode for an entire PCB sign-off simulation.
The Signal Integrity service can be used as a standalone service or as part of a larger PCB design project depending on the requirements.