Many of today's digital designs incorporate H.D.I. technologies that enforce complex strategies to maintain signal quality and reliability. High speed data interfaces such as DDR and PCI Express impose complex timing demands that can no longer be resolved using traditional methods.
CADSTAR Signal Integrity Verify (SIV) offers a complete pre- and post-layout Signal Integrity toolset that enable the engineer to organise, constraint, explore and analyse their design to reduce the number of prototypes and minimise both risk and cost.
Seamlessly integrated into the CADSTAR Design suite, CADSTAR SIV utilises the Constraint Manager spreadsheet-style interface that simplifies design navigation and constraint entry for High Speed, Signal Integrity and Power Integrity Analysis. The graphical Scenario Editor lets you explore alternate design strategies to assess the best approach to meet your design objectives, then model a virtual prototype using IBIS models or generic devices to evaluate termination styles and net topologies.
Interactive / Batch Simulation
CADSTAR SIV works in both time- and frequency- domain modes to analyse transmission lines parameters, provide fast analysis of reflection and crosstalk, and measure timing and delay characteristics. The simulator provides a range of results including Impedance, Coupled line, S-Parameter, Fast Fourier Transformation and Eye Diagrams, while automatic signal evaluation provides a full range of numeric data points. Experiment with passive device values or transmission line length using Parameter Sweep to determine optimal values. Passive SPICE models can also be used and equivalent circuit models can be created to model passive parasitic devices.
Layer Stack Definition
The layer stack can be modelled to determine the characteristic impedance of critical transmission lines, accommodating track profile and advanced construction materials to achieve more accurate results. Frequency-dependent losses are accommodated for enhanced accuracy at higher frequencies.