CADSTAR for High Speed Design Specialists

Why is High Speed Important?

To meet the growing demand for smaller, faster, more powerful products, IC vendors deliver complex devices that require special consideration of track length, skew, noise immunity and Signal Integrity. Implementing these devices in your products requires an increasing knowledge of constraint-driven High-Speed design techniques and an in-depth understanding of the science and technology of signal propogation.

The CADSTAR High Speed Design suite has been designed to address this challenge, offering you an integrated design environment where constraint entry, verification, analysis and simulation can be performed in one environment.

Constraint Management

Central to this technology is the Constraint Manager, a powerful constraint-entry and analysis tool that is instantly familiar to every engineer, utilising the industry standard spreadsheet interface. The designer can enter either length- or delay-based constraints as required, and net topologies can be determined automatically from the device models specified in the CADSTAR library. You can instantly review the results of these changes on the signal integrity of the design, then make informed choices on the best approach to avoid problems.

Based on your PCB layout, Constraint Manager can automatically allocate nets into various item types including Power, Busses and Differential Pairs. Groups of nets, such as a data bus or byte lane, can then be assigned a collective constraint such as a skew or maximum length. 

Routing Options

The CADSTAR P.R.Editor High Speed routing tools accommodate all constraints yet allow the designer the flexibility to temporarily override DRC rules, choose how to display constraint markers, whether push-aside and auto-cleanup are required, and a host of other options.

Depending on the complexity of the design and the types of devices used, you can switch to delay-based rules where the router uses IBIS device models and a field solver solution to provide an enhanced 3D simulation of the board, enabling accurate calculation of impedance and timing characteristics.

Exploration

You have the option to explore signal integrity with CADSTAR SIV at the conceptual level, even before the net has been routed, to determine termination strategies and the impact of alternate topologies. A range of Scenarios can be explored and saved for later review, including analysis of sweeping design parameters and generation of eye diagrams.

Once the nets have been routed the designer can run an in-place simulation simply by selection of the net within the routing environment, saving time and ensuring his focus remains on the current design elements.

Power Plane analysis

As the number of power rails increases and their values continue to decrease, the ability of planes within a design to distribute power to those devices that need it can be seriously degraded by both the physical definition of the plane and the distribution of decoupling. CADSTAR Power Integrity Advance helps you determine the level of risk to your PCB and through analysis of the planes guides you to resolve the power distribution problem.