CADSTAR for Electronic Design Engineers
Your PCB design challenges require innovative solutions, so being able to capture them in a fast, effective, error-free manner is critical. CADSTAR Schematic provides you with a flexible, yet powerful, design platform that includes:
- your choice of design methodology that lets you design at the Symbol, Part, Block or Sheet level with a multi-layer hierarchical or multi-sheet design environment
an intelligent connective database that accurately captures your design intent and maintains design integrity throughout the CADSTAR flow
a fully customisable design environment with the same GUI in Schematic, PCB Layout, Library Editor and Routing environments
a range of tools to help you define, simulate and manage your design data
Libraries are key to the design process, so Zuken gets you ahead of the game with an on-line library of more than 250,000 parts from leading vendors such as Actel, Analog Devices, Intel, Texas and Zetex. You can add dynamic links to a supplier's datasheet or web site to provide the engineer with the latest information at their fingertips.
If you need to integrate CAD data with your Engineering database CADSTAR supports access to your ODBC compliant data source, enabling not just a link to the latest corporate information but also the ability to run parametric search to locate the right part by a range of attributes. Link each part to the vendors web site or your own datasheet library to put more power at the fingertips of the design engineer.
Need to include repeated or pre-defined 'golden circuit' design blocks? Create them as ReUse blocks and build your own library for you and your colleagues to share. ReUse blocks in Schematics can link automatically to ReUse blocks in PCB Layout, helping you save on the time taken during layout and test.
And all of this comes standard with every version of CADSTAR...
A growing number of designs include programmable devices that let you extend and customise the functionality of your designs. Today's high capacity devices have high pin counts that make symbol definition and management of pin connectivity increasingly complex, not just in the Schematic but throughout the design process.
CADSTAR FPGA, founded on industry-leading technology from Aldec Inc, enables FPGA development, synthesis and verification using a vendor-independent intuitive design methodology. Single-click transfer of pin information to and from CADSTAR allows fast, efficient creation of functional block symbols and synchronisation of pin changes that may be required to optimise the layout at the PCB layout.
CADSTAR supports tools for Analog, Digital and mixed mode simulation. You can export a Spice netlist for simulation in your own tool, or take advantage of the automatic transfer of your Schematic data to the B2Spice A/D simulator.
B2 Spice A/D provides a range of powerful capabilities that reach new standards in ease-of-use, power, and capability.
Variant Manager allows you to define market-specific products that broaden the scope and appeal of your range, improve cost control and enhance product differentiation. CADSTAR allows you to simply create, view and list several design variants by excluding selected items or specifying alternate parts.
Constraint Driven Design
Even the most straightforward modern processor and memory combination uses a DDR interface, so it makes sense to add the criticial pin, net and timing constraints directly into the Schematic. The CADSTAR Constraint Browser provides the ideal environment for entering and managing even the most complex rules, using a familiar spreadsheet style interface that helps you capture and document design intent.
Placement of design blocks or even individual components gets important as noise margins are reduced and switching speeds increase, so CADSTAR Placement Planner offers a full suite of Placement and board setup utilities (e.g. Layer Stackup, Design Rules, etc.) to provide the Design Engineer with the tools to define crticial placement.
Already using CADSTAR Schematic for high speed design and rules entry? Watch the video for a brief tutorial on how to migrate to Constraint Browser for fast, efficient, accurate rules definition.