CADSTAR Signal Integrity Verify

Many of today's digital designs incorporate ‘High-Speed’ technologies that require complex strategies to maintain Signal Integrity and reliability. Continuous advances in I.C. technology, interconnect strategies and packaging density requires
engineers to work more efficiently than ever before to minimise risk and shrink development cycles.

High speed interfaces such as DDR and PCI Express impose complex timing demands that can no longer be resolved using traditional methods.

CADSTAR Signal Integrity Verify (SIV) offers a complete pre- and post-layout Signal Integrity toolset that enable the engineer to organise, constraint, explore and analyse their design to reduce the number of prototypes and minimise cost.

Key Benefits

Design Navigation

Seamlessly integrated into the CADSTAR Design suite, CADSTAR SIV utilises the Constraint Manager spreadsheet-style interface that simplifies design navigation and constraint entry for High Speed, Signal Integrity and Power Integrity Analysis.

The graphical Scenario Editor lets you explore alternate design strategies to assess the best approach to meet your design objectives. You can model a virtual prototype using vendor-supplied IBIS models, or generic devices from the built-in library, to evaluate different termination styles and net topologies to achieve the optimum design.

Interactive / Batch Simulation

CADSTAR SIV works in both time- and frequency- domain modes to analyze transmission lines parameters, provide fast analysis of reflection and crosstalk, and measure timing and delay characteristics. You have the option of Interactive or Batch modes, returning a range of results including Impedance, Coupled line, S-Parameter, Fast Fourier Transformation and Eye Diagrams, while automatic signal evaluation provides a full range of numeric data points.

Experiment with passive device values or transmission line length using Parameter Sweep to determine optimal values. Passive SPICE models can also be used and equivalent circuit models can be created to model passive parasitic devices.

Layer Stack Definition

The layer stack can be modelled to determine the characteristic impedance of critical transmission lines, accommodating track profile (trapezoid) and advanced construction materials to achieve more accurate results. Frequency-dependent losses are accommodated for enhanced accuracy at higher frequencies.