CADSTAR Place & Route Editor

Refined Technology

Zuken has been at the forefront of PCB Layout and routing technology for over three decades, providing tools that significantly reduce design cycle time and increase productivity.

With a mix of manual, auto-interactive and automatic tools for PCB Placement and Routing, CADSTAR Place & Route Editor has been optimised for performance, quality and design manufacturability.

Capacity and Capability

Employing a gridless architecture and unlimited layer design capacity, Place & Route Editor can meet today’s advanced technology design challenges, including DDR2, DDR3 and PCI Express, with ease.

An extensive set of design rules lets you configure the system to meet your specific technical requirements, while Area rules and High Speed constraints easily accommodate the complex matrix of timing rules found in today’s high performance designs.

Benefits

Intelligent Component Placement

Visual indicators guide you towards optimum placement that conforms to pre-defined constraints. Components can be dynamically pushed aside, aligned with other devices or spread to fill the available space. You can cross-probe selections from CADSTAR Schematic to enable a truly engineer-driven placement process with Constraint Browser.

Routing with Power and Control

Experienced PCB Designers choose to route critical areas by hand, Place & Route Editor offers full control of the manual routing process with a choice of DRC modes and direct access to a range of tools via shortcuts or mouse menus. Connectivity can be optimised on-the-fly for Pin Swap, based on pin data from the library. Routing can be constrained to any layer set, with automatic connection of power nets to full or partial planes.

Activ-45 mode is the ultimate for speed and precision, offering single-click routing with auto completion; with dynamic push-aside, springback and segment break enabled you have the power to complete even the most complex layout.

Advanced Routing Options

A range of advanced routing algorithms for bus pattern, memory, mitre, river and minimum-impact routing are included to address specific challenges. The fanout router creates intelligent breakout patterns from dense SMT footprints, including spiral via patterns, to simplify subsequent routing on inner layers.

Any selection of nets can be autorouted using the multipass router, which maximises routing completion by running sequential route and optimisation passes to achieve highest density.

High-Speed Routing

Place & Route Editor HS obeys a wide range of fast circuit rules including min/max length, skew, delay and crosstalk limits. The integrated Constraint Manager imports rules & constraints direct from the Schematic, providing a smooth error-free transfer of data from Engineer to Layout specialist.  An array of verification tools enables pre- and post-route analysis of crosstalk, impedance and IC rules.

Manufacturing Considerations

Optimisation of the layout to minimise overall track length, reduce the number of vias and improve manufacturability can all be run on demand, with options for track fattening, addition of teardrops and acid trap removal. Testpoints can be allocated to existing design features (pads and vias) or inserted as user-defined Testpoint elements.