CADSTAR Place & Route Editor
Zuken has been at the forefront of PCB Layout and routing technology for over three decades, providing tools that significantly reduce design cycle time and increase productivity.
With a mix of manual, auto-interactive and automatic tools for PCB Placement and Routing, CADSTAR Place & Route Editor has been optimised for performance, quality and design manufacturability.
Capacity and Capability
Employing a gridless architecture and unlimited layer design capacity, Place & Route Editor can meet today’s advanced technology design challenges, including DDR2, DDR3 and PCI Express, with ease.
An extensive set of design rules lets you configure the system to meet your specific technical requirements, while Area rules and High Speed constraints easily accommodate the complex matrix of timing rules found in today’s high performance designs.
- Dedicated Place & Route environment optimised for speed and accuracy
- Direct integration with CADSTAR Design Editor enables cross-probing to both Schematic and PCB Layout
- High capacity yet light on resources
- Advanced interactive and automatic routing functionality supports a broad range of advanced design technologies
- Constraint driven for ‘right by design’ High Speed layout
Intelligent Component Placement
Visual indicators guide you towards optimum placement that conforms to pre-defined constraints. Components can be dynamically pushed aside, aligned with other devices or spread to fill the available space. You can cross-probe selections from CADSTAR Schematic to enable a truly engineer-driven placement process with Constraint Browser.
Routing with Power and Control
Experienced PCB Designers choose to route critical areas by hand, Place & Route Editor offers full control of the manual routing process with a choice of DRC modes and direct access to a range of tools via shortcuts or mouse menus. Connectivity can be optimised on-the-fly for Pin Swap, based on pin data from the library. Routing can be constrained to any layer set, with automatic connection of power nets to full or partial planes.
Activ-45 mode is the ultimate for speed and precision, offering single-click routing with auto completion; with dynamic push-aside, springback and segment break enabled you have the power to complete even the most complex layout.
Advanced Routing Options
A range of advanced routing algorithms for bus pattern, memory, mitre, river and minimum-impact routing are included to address specific challenges. The fanout router creates intelligent breakout patterns from dense SMT footprints, including spiral via patterns, to simplify subsequent routing on inner layers.
Any selection of nets can be autorouted using the multipass router, which maximises routing completion by running sequential route and optimisation passes to achieve highest density.
Place & Route Editor HS obeys a wide range of fast circuit rules including min/max length, skew, delay and crosstalk limits. The integrated Constraint Manager imports rules & constraints direct from the Schematic, providing a smooth error-free transfer of data from Engineer to Layout specialist. An array of verification tools enables pre- and post-route analysis of crosstalk, impedance and IC rules.
Optimisation of the layout to minimise overall track length, reduce the number of vias and improve manufacturability can all be run on demand, with options for track fattening, addition of teardrops and acid trap removal. Testpoints can be allocated to existing design features (pads and vias) or inserted as user-defined Testpoint elements.
CADSTAR PREditor - Key Features
- Component move, rotate, swap and align with push-aside, springback, minimum force indicators and on-line DRC
- Any-angle manual, auto-interactive and automatic routing with on-line DRC, plus Activ-45 ‘one click’ router
- Up to 255 layers plus support for single layer design with wire Jumpers
- Push-aside, slide-along & springback routing controls
- Orthogonal or Curved routes
- Bus, Memory, River and Fanout routing
- Dynamic copper pour with auto-flood
- Testpoint analysis & creation
- Macro and Scripting interfaces
- Electrical Net (eNet) structures
- Layer Impedance Calculator with Field Solver and Template configurator
- Length or Delay constraints with Minimum, Maximum and Skew control of Differential Pairs, Busses, Nets, Pin Pairs and more ...
- Configure Net Topology (H-Tree, Star, Daisy, Chain, etc.)
- Automatic Differential Pairs generator
- Crosstalk analysis
- Direct integration with Signal and Power Integrity analysis