CADSTAR SI Verify
According to industry consultants, over 80% of multi-layer PCB designs are high-speed, needing special design strategies addressing high-speed effects to ensure successful operation. This trend will continue in the coming years with the introduction of new low voltage technologies, increased board density, faster edge rates, and shorter development cycles. To meet this challenge, the users have to adopt new methodologies to ensure the designs will work as desired, fulfilling all signal quality and timing demands. Working to old 'rules of thumb' will no-longer be adequate to meet these requirements, so in order to be successful, the users have to adopt new tools that have simulation capabilities.
CADSTAR SI Verify offers a complete pre and post-layout signal integrity simulation toolset, seamlessly integrated into CADSTAR. It uses an accurate transmission line simulation approach to analyze reflection and crosstalk effects, and to calculate the relevant timing information and delays. It can be used interactively by the user for selected nets as well as in batch-mode for an entire PCB sign-off simulation.
The required electrical parameters of transmission lines (phase velocity, inductance and capacitance matrices, characteristic impedances) are determined by a 2D field solver using boundary element methods. The time domain signal integrity simulation offers a fast calculation of reflection and crosstalk effects on printed circuit boards, considering also the non-linear characteristics of terminations.
